A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-μm Pitch

被引：20

作者：

Podpod, A. ^{[1
]}

Slabbekoorn, J. ^{[1
]}

Phommahaxay, A. ^{[1
]}

Duval, F. ^{[1
]}

Salahouedlhadj, A. ^{[1
]}

Gonzalez, M. ^{[1
]}

Rebibis, K. ^{[1
]}

Miller, R. A. ^{[1
]}

Beyer, G. ^{[1
]}

Beyne, E. ^{[1
]}

机构：

[1] Interuniv Microelect Ctr IMEC, Leuven, Belgium

来源：

2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) | 2018年

关键词：

component; Fan-Out; Wafer Level Package; Heterogenous Integration; Flip-Chip; warpage; die shift; wafer molding; ultra high density;

D O I：

10.1109/ECTC.2018.00063

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The rapid growth of data bandwidth required between logic and memory chips for next generation device nodes is progressively pushing low I/O count serial busses to their limits. To further satisfy this increasing need for high data rates, wider I/O count busses are now being developed and established. Over the past years, various Fan-Out Wafer-Level-Packaging (FOWLP) approaches have been developed to answer the needs mentioned above and the increasingly demanding function integration on package. Imec has been working on a novel 300mm Fan-Out Wafer-Level-Packaging concept that enables 20 mu m pitch interconnect density. Results from experiments demonstrates wafer bow below 500 mu m after molding on silicon substrate with ultra-low die shift with maximum die to carrier mismatch below 10 mu m on full 300mm wafers. Further warpage and die shift evolution are expected depending on the process steps the wafers must go through and will be further discussed.

引用

页码：370 / 378

页数：9