A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-μm Pitch

The rapid growth of data bandwidth required between logic and memory chips for next generation device nodes is progressively pushing low I/O count serial busses to their limits. To further satisfy this increasing need for high data rates, wider I/O count busses are now being developed and established. Over the past years, various Fan-Out Wafer-Level-Packaging (FOWLP) approaches have been developed to answer the needs mentioned above and the increasingly demanding function integration on package. Imec has been working on a novel 300mm Fan-Out Wafer-Level-Packaging concept that enables 20 mu m pitch interconnect density. Results from experiments demonstrates wafer bow below 500 mu m after molding on silicon substrate with ultra-low die shift with maximum die to carrier mismatch below 10 mu m on full 300mm wafers. Further warpage and die shift evolution are expected depending on the process steps the wafers must go through and will be further discussed.