Thermomechanical Stress-Aware Management for 3-D IC Designs

Thermal characteristics have been considered as one of the most challenging problems in 3-D integrated circuits (3-D ICs). Due to the thermal expansion coefficient mismatch between through-silicon vias (TSVs) and the silicon substrate, and the presence of elevated thermal gradients, thermomechanical stress issues are exacerbated in 3-D ICs. In this brief, we propose a solution that combines design-time and runtime techniques to reduce thermomechanical stress and the associated reliability issues. A TSV stress-aware floorplan policy is proposed to minimize the possibility of wafer cracking and interfacial delamination. In addition, a run-time thermal management scheme effectively eliminates large thermal gradients between layers. Experimental results show that the reliability of 3-D design can be significantly improved due to the reduced TSV thermal load and the elimination of mechanical damaging thermal cycling pattern. Moreover, impacts of thermal characteristics in TSVs and thermal vias insertion are explored.