Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based MMSE Detector for Massive MIMO Systems

被引:37
|
作者
Liu, Leibo [1 ]
Peng, Guiqiang [1 ]
Wang, Pan [1 ]
Zhou, Sheng [2 ]
Wei, Qiushi [1 ]
Yin, Shouyi [1 ]
Wei, Shaojun [1 ]
机构
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
[2] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
基金
中国国家自然科学基金; 国家重点研发计划;
关键词
Massive multiple-input multiple-output (MIMO); detection; minimum mean square error (MMSE); recursive conjugate gradient; very-large-scale integration (VLSI); wireless communications; SEARCH; ALGORITHM; WIRELESS; DESIGN;
D O I
10.1109/TSP.2020.2964234
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Minimum-mean-square-error (MMSE) detection is increasingly relevant for massive multiple-input multiple-output (MIMO) systems. MMSE suffers from high computational complexity and low parallelism because of the increasing number of users and antennas in massive MIMO systems. This paper proposes a recursive conjugate gradient (RCG) method to iteratively estimate signals. First, a recursive conjugate gradient detection algorithm is proposed that achieves high parallelism and low complexity through iteration. Second, a quadrant-certain-based initial method that improves detection accuracy without added complexity is proposed. Third, an approximated log likelihood ratio (LLR) computation method is proposed to achieve simplified calculation. The analyses show that compared with related methods, the proposed RCG algorithm reduces computational complexity and exploits the potential parallelism. RCG is mathematically demonstrated to achieve low approximated error. Based on the RCG method, an architecture is proposed in a 64-QAM massive MIMO system. First, a parallel processing element array with single-sided input is adopted; this array eliminates the throughput limitation. Second, a deeply pipelined user-level method based on the recursive conjugate gradient method is proposed. Third, an approximated architecture is proposed to compute the soft output. The architecture is verified on an FPGA and fabricated on with TSMC 65 CMOS technology. The chip achieves 2.6 energy efficiency (throughput/power) and area efficiency (throughput/area), respectively, which are 2.39 to 10.60 those of the normalized state-of-the-art designs.
引用
收藏
页码:573 / 588
页数:16
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