Crosstalk- and SEU-aware networks on chips

被引:25
作者
Frantz, Arthur Pereira
Cassel, Maico
Kastensmidt, Fernanda Lima
Cota, Erika
Carro, Luigi
机构
[1] Univ Fed Rio Grande do Sul, Inst Informat, PPGC, BR-91501970 Porto Alegre, RS, Brazil
[2] Univ Fed Rio Grande do Sul, Dept Comp Sci, Porto Alegre, RS, Brazil
来源
IEEE DESIGN & TEST OF COMPUTERS | 2007年 / 24卷 / 04期
关键词
D O I
10.1109/MDT.2007.128
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article proposes the use of mixed hardware-software solutions to simultaneously address crosstalk faults and single-event upsets in on-chip networks. After analyzing the susceptibility of routers to these faults, the authors propose a software-based solution to deal with SEUs. But they show that the effect of crosstalk faults can be corrected only through hardware-based solutions. The authors then discuss four approaches that combine the use of hardware and software mitigation techniques to simultaneously deal with SEU and crosstalk effects in NoC routers. Experimental results show that the mixed hardware-software strategy is a cost-effective solution, even in high soft-error-rate environments. © 2007 IEEE.
引用
收藏
页码:340 / 350
页数:11
相关论文
共 10 条
  • [1] Acquaviva A, 2003, LECT NOTES COMPUT SC, V2799, P540
  • [2] Low power error resilient encoding for on-chip data buses
    Bertozzi, D
    Benini, L
    De Micheli, G
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, : 102 - 109
  • [3] CUVIELLO M, 1999, P INT C COMP AID DES, P297
  • [4] FRANTZ AP, 2006, P IEEE INT TEST C IT
  • [5] Robust system design with built-in soft-error resilience
    Mitra, S
    Seifert, N
    Zhang, M
    Shi, Q
    Kim, KS
    [J]. COMPUTER, 2005, 38 (02) : 43 - +
  • [6] Design for soft error mitigation
    Nicolaidis, M
    [J]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (03) : 405 - 418
  • [7] Coding techniques for low switching noise in fault tolerant busses
    Nieuwland, AK
    Katoch, A
    Rossi, D
    Metra, C
    [J]. 11TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, 2005, : 183 - 189
  • [8] ROSSIER J, 2001, PSYCHOL PSYCHOMETRIE, V22, P59
  • [9] Performance driven reliable link design for networks on chips
    Tamhankar, Rutuparna Ramesh
    Murali, Srinivasan
    De Micheli, Giovanni
    [J]. ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 749 - 754
  • [10] SoCIN: A parametric and scalable network-on-chip
    Zeferino, CA
    Susin, AA
    [J]. 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS, 2003, : 169 - 174