Fully Utilized and Low Design Effort Architecture for H.264/AVC Intra Predictor Generation

Fully exploiting the spatial feature of image makes H.264/AVC standard superior in intra prediction part. However, when hardware is considered, full support of all intra modes will cause high design effort, especially for large image size. In this paper, we propose a low design effort solution for intra predictor generation, which is the most significant part in intra engine. Firstly, one parallel processing flow is given out, which achieves 37.5% reduction of processing time. Secondly, a fully utilized predictor generation architecture is given out, which saves 77.5% cycles of original one. With 30.11k gates at 200MHz, our design can support full-mode intra prediction for real-time processing of 4k x 2k@60fps.