Structural design of a CMOS full low dropout voltage regulator

被引：5

作者：

Filanovsky, I. M. ^{[1
]}

Reja, Mahbub ^{[2
]}

Ivanov, V. ^{[3
]}

机构：

[1] Univ Alberta, Edmonton, AB, Canada

[2] Scanimetr Inc, Edmonton, AB, Canada

[3] Texas Instruments Inc, Tucson, AZ USA

来源：

2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4 | 2007年

关键词：

D O I：

10.1109/ICECS.2007.4511103

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper describes structural design of a full (complete) low dropout (LDO) voltage regulator. This LDO is using the following basic subcircuits: bandgap reference (BGR), folded-cascode current operational amplifier (COA), and bins circuit. The regulator is divided in three main blocks, namely, a sub-regulator generating power supply voltage for the BGR, a scaling amplifier providing convenient reference voltage for the LDO, and the LDO itself providing the required output voltage. Each block is consisting of a COA, pass transistor and resistor and represents a dedicated feedback loop. The regulator does not require any on-chip compensation capacitors, and ensures stable operation for a very wide range of capacitive loads. The complete LDO regulator is realized in standard digital 0.13-mu m CMOS process for the output voltage of 1.22 V from 1.8-3.3 V power supply.

引用

页码：763 / +

页数：2

共 8 条

[1]

AHMADI MM, 2005, P 48 MIDW S CIRC SYS, V2, P998

[2] A frequency compensation scheme for LDO voltage regulators [J].