A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture

被引：14

作者：

Fujibayashi, M ^{[1
]}

Nozawa, T

Nakayama, T

Mochizuki, K

Konda, M

Kotani, K

Sugawa, S

Ohmi, T

机构：

[1] Tohoku Univ, Grad Sch Engn, Dept Elect Engn, Sendai, Miyagi 9808579, Japan

[2] Tohoku Univ, New Ind Creat Hatchery Ctr, Sendai, Miyagi 9808579, Japan

[3] Tohoku Univ, Grad Sch Engn, Management Sci & Technol Dept, Sendai, Miyagi 9808579, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 05期

关键词：

high-resolution still-image compression; image compression; vector quantization;

D O I：

10.1109/JSSC.2003.810064

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A still-image encoder based on vector quantization (VQ) has been developed using 0.35-mum triple-metal CMOS technology for encoding a high-resolution, still image. The chip employs the needless calculation elimination method and the adaptive resolution VQ (AR-VQ) technique. The needless calculation elimination method can reduce computational cost of VQ encoding to 40% or less of the full-search VQ encoding, while maintaining the accuracy of full-search VQ. AR-VQ realizes a compression ratio of over 1/200 while maintaining image quality. The processor can compress a still image of 1600 x 2400 pixels within 1 s and operates at 66 MHz with power dissipation of 660 mW under 2.5-V power supply, which is 1000 times larger performance per unit power dissipation than the software implementation on current PCs.

引用

页码：726 / 733

页数：8

共 30 条

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