CMOS RF Power Amplifier Variability and Reliability Resilient Biasing Design and Analysis

被引:14
作者
Liu, Yidong [1 ]
Yuan, Jiann-Shiun [1 ]
机构
[1] Univ Cent Florida, Sch Elect Engn & Comp Sci, Orlando, FL 32816 USA
关键词
Hot electron; Monte Carlo simulation; positive bias temperature instability (PBTI); power amplifier (PA); random doping fluctuation; reliability; variability; INTERFACE-TRAP GENERATION; MOS DEVICES; DEGRADATION; BREAKDOWN; SUBJECT; PBTI; NBTI;
D O I
10.1109/TED.2010.2093141
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a novel biasing design that makes the complementary metal-oxide-semiconductor radio frequency power amplifier (PA) resilient to process variability and device reliability. The biasing scheme provides resilience through the threshold voltage adjustment, and at the mean time, it does not degrade the PA performance. Analytical equations are derived for studying the resilient biasing on PA process sensitivity. A class-AB PA with a resilient design is compared with a PA without such a design using a Predictive Technology Model 65-nm technology. The Advanced Design System simulation results show that the resilient biasing design helps improve the robustness of the PA in P-1dB, P-sat, and power-added efficiency. Except for postfabrication calibration capability, the adaptive body biasing design reduces the impact of variability and reliability on PA significantly when subjected to threshold voltage shift and electron mobility degradation.
引用
收藏
页码:540 / 546
页数:7
相关论文
共 22 条
[1]   Penelope :: The NBTI-Aware processor [J].
Abella, Jaume ;
Vera, Xavier ;
Gonzalez, Antonio .
MICRO-40: PROCEEDINGS OF THE 40TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2007, :85-+
[2]  
Abrishami Hamed., 2008, GLSVLSI 08, P29
[3]  
[Anonymous], 03024377ATR INT SEM
[4]   A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration [J].
Chen, Tao ;
Gielen, Georges G. E. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (11) :2386-2394
[5]   On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing [J].
Chen, Z ;
Hess, K ;
Lee, JJ ;
Lyding, JW ;
Rosenbaum, E ;
Kizilyalli, I ;
Chetlur, S ;
Huang, R .
IEEE ELECTRON DEVICE LETTERS, 2000, 21 (01) :24-26
[6]   CMOS 6-T SRAM cell design subject to ''atomistic" fluctuations [J].
Cheng, B. ;
Roy, S. ;
Asenov, A. .
SOLID-STATE ELECTRONICS, 2007, 51 (04) :565-571
[7]   Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide [J].
Denais, M ;
Huard, V ;
Parthasarathy, C ;
Ribes, G ;
Perrier, F ;
Revil, N ;
Bravaix, A .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (04) :715-722
[8]   Soft breakdown of ultra-thin gate oxide layers [J].
Depas, M ;
Nigam, T ;
Heyns, MM .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (09) :1499-1504
[9]  
Dierickx B., 2007, SCALING 90 NM DESIGN
[10]   NBTI degradation: From physical mechanisms to modelling [J].
Huard, V ;
Denais, M ;
Parthasarathy, C .
MICROELECTRONICS RELIABILITY, 2006, 46 (01) :1-23