Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization

Worst-case dI/dt voltage noise is typically characterized post-silicon using direct voltage measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad resources or suffer from design-time and run-time overheads. This work proposes an alternative non-intrusive, zero-overhead approach for post-silicon dI/dt voltage noise characterization based on sensing CPU electromagnetic emanations using an antenna and a spectrum analyzer. This approach is based on the observation that high amplitude electromagnetic emanations are correlated with high resonance-induced voltage-noise. This approach enables essential Power-Delivery Network characterization tasks such as: a) obtaining the first-order resonance-frequency of the Power-Delivery LC-tank network, and b) automatically generating voltage noise (dI/dt) stress tests with a genetic-algorithm that is driven by the electromagnetic signal amplitude. The generality of the approach is established by successfully applying it to four different CPUs: two ARM multi-core mobile CPU clusters hosted on a big.LITTLE configuration, one x86-64 AMD desktop CPU and one ARM 64bit 8-core clustered architecture server CPU. The efficacy of the proposed methodology is validated through V-MIN and direct voltage-noise measurements. Furthermore, the effectiveness of the EM approach to generate dI/dt viruses that have higher V-MIN that conventional workloads is demonstrated with a dynamic-voltage-scaling (DVS) governor that scales the voltage according to the V-MIN of the EM generated dI/dt viruses for various core-allocations scenarios. For a 62-hour test with a varying workload mix and core allocations, this governor provides safe below nominal-voltage operation.