On the input common-mode voltage range of CMOS bulk-driven input stages

被引:21
作者
Carrillo, Juan M. [1 ]
Torelli, Guido [2 ]
Dominguez, Miguel A. [1 ]
Francisco Duque-Carrillo, J. [1 ]
机构
[1] Univ Extremadura, Dept Elect, E-06071 Badajoz, Spain
[2] Univ Pavia, Dept Elect, I-27100 Pavia, Italy
关键词
bulk-driven MOS transistors; CMOS analog integrated circuits; low-voltage; operational transconductance amplifiers; OTA-C filters; TO-RAIL INPUT; OPERATIONAL-AMPLIFIER; DESIGN; CIRCUIT; OPAMP; OTA;
D O I
10.1002/cta.667
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper the response of a bulk-driven MOS Metal-Oxide-Semiconductor input stage over the input common-mode voltage range is discussed and experimentally evaluated. In particular, the behavior of the effective input transconductance and the input current is studied for different gate bias voltages of the input transistors. A comparison between simulated and measured results, in standard 0.35-m CMOS Complementary Metal-Oxide-Semiconductor technology, demonstrates that the model of the MOS transistors is not sufficiently accurate for devices operating under forward bias conditions of their source-bulk pn junction. Therefore, the fabrication and the experimental evaluation of any solution based on this approach are highly recommended. A technique to automatically control the gate bias voltage of a bulk-driven differential pair is proposed to optimize the design tradeoff between the effective input transconductance and the input current. The proposed input stage was integrated as a standalone block and was also included in a 1.5-V second-order operational transconductance amplifier (OTA)-C lowpass filter. Experimental results validate the effectiveness of the approach. Copyright (C) 2010 John Wiley & Sons, Ltd.
引用
收藏
页码:649 / 664
页数:16
相关论文
共 37 条
[1]  
ALLEN PE, 1995, ISSCC DIG TECH PAP I, V38, P192, DOI 10.1109/ISSCC.1995.535518
[2]  
Allen PhillipE., 2002, CMOS ANALOG CIRCUIT, V2nd
[3]  
[Anonymous], P IEEE SW S MIX SIGN
[4]  
BAHMANI F, 2000, P IEEE INT S CIRC SY, V2, P669
[5]   Designing 1-V OP amps using standard digital CMOS technology [J].
Blalock, BJ ;
Allen, PE ;
Rincon-Mora, GA .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (07) :769-780
[6]  
BLALOCK BJ, 1996, P ISCAS, V1, P305
[7]   Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries [J].
Carrillo, JM ;
Duque-Carrillo, JF ;
Torelli, G ;
Ausín, JL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (08) :1364-1372
[8]  
CARRILLO JM, 2008, P IEEE INT C EL CIRC, P13
[9]   1-V rail-to-rail CMOS OpAmp with improved bulk-driven input stage [J].
Carrillo, Juan M. ;
Torelli, Guido ;
Perez-Aloe, Raquel ;
Duque-Carrillo, J. Francisco .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (03) :508-517
[10]   Input Common-Mode Voltage Behaviour of CMOS Bulk-Driven Differential Stages [J].
Carrillo, Juan M. ;
Dominguez, Miguel A. ;
Francisco Duque-Carrillo, J. ;
Torelli, Guido .
2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2, 2009, :267-+