A Low Power Schmitt Trigger Design using SBT technique in 180nm CMOS Technology

被引：0

作者：

Suresh, Ambothu ^{[1
]}

机构：

[1] Natl Inst Technol Kurukshetra, Sch VLSI Design & Embedded Syst, Kurukshetra, Haryana, India

来源：

2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT) | 2014年

关键词：

Schmitt trigger; hysteresis; aspect ratio; propagation delay; low power; leakage reduction;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents the effect of source voltage and load capacitance on the performance of CMOS Schmitt Trigger circuit with self-bias transistor (SBT) technique which was used to reduce power. The CMOS Schmitt Trigger circuit was modified by designing the transistors aspect ratio on the basis of conventional CMOS Schmitt Trigger and it is implemented using CADENCE Virtuoso in Spectra Simulator using UMC-180nm technology for different modified design. Results are compared in terms of propagation delay, power, and energy-delay product. From the simulation results, the modified CMOS Schmitt Trigger was able to operate between 0.8V to 1.5V voltage range.

引用

页码：533 / 536

页数：4

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