Detection and repair of radiation induced single event upsets in an FPGA-based readout for TES bolometer arrays

被引:0
作者
Smecher, Graeme [1 ]
Aubin, Francois [1 ]
Djazovski, Oleg [3 ]
Dobbs, Matt [1 ]
Faulkner, Gordon [2 ]
Gulino, Fabio [2 ]
Hyland, Peter O. [1 ]
MacDermid, Kevin [1 ]
Rowlands, Neil [2 ]
机构
[1] McGill Univ, Montreal, PQ, Canada
[2] COM DEV Int, Cambridge, ON, Canada
[3] Canadian Space Agcy, St Hubert, PQ, Canada
来源
MILLIMETER, SUBMILLIMETER, AND FAR-INFRARED DETECTORS AND INSTRUMENTATION FOR ASTRONOMY V | 2010年 / 7741卷
基金
加拿大自然科学与工程研究理事会;
关键词
FPGA; Single Event Upset (SEU) mitigation; radiation hardening; SEU MITIGATION; DESIGN; TMR;
D O I
10.1117/12.858201
中图分类号
P1 [天文学];
学科分类号
0704 ;
摘要
Frequency multiplexed readout systems for large TES bolometer arrays are in use for ground and balloon-based mm-wavelength telescopes. New digital backend electronics for these systems implement advanced signal processing algorithms on FPGAs. Future satellite instruments will likely use similar technology. We address the challenges of operating FPGAs in an orbital radiation environment using neighbour-neighbour monitoring, where each FPGA monitors its neighbour and can correct errors due to radiation events. This approach reduces the FPGA's susceptibility to crippling events without relying on triple redundancy or radiation-hardened parts, which raise the system cost, power budget, and complexity. This approach also permits earlier adoption of the latest FPGAs, since radiation-hardened variants typically lag the state of the art.
引用
收藏
页数:9
相关论文
共 24 条
[1]   SEU sensitivity of Virtex configuration logic [J].
Alderighi, M ;
Candelori, A ;
Casini, F ;
D'Angelo, S ;
Mancini, M ;
Paccagnella, A ;
Pastore, S ;
Sechi, GR .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, 52 (06) :2462-2467
[2]  
Allen G., 2008, Virtex-4QV Static SEU Characterization Summary
[3]  
[Anonymous], VIRTEX 4VQ DYNAMIC M
[4]  
[Anonymous], 2008, VIRTEX 4 FPGA USER G
[5]  
[Anonymous], 2020, MICROBLAZE PROC REF
[6]   Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis [J].
Berg, Melanie ;
Poivey, C. ;
Petrick, D. ;
Espinosa, D. ;
Lesea, Austin ;
LaBel, K. A. ;
Friendlich, M. ;
Kim, H. ;
Phan, Anthony .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, 55 (04) :2259-2266
[7]  
Bridgford B., 2008, SINGLE EVENT UPSET M
[8]  
Carlstrom J.E., 2009, The 10 Meter South Pole Telescope
[9]  
Carmichael C., 2008, Correcting single-event upsets in virtex-4 platform fpga configuration
[10]  
Carmichael C., 2009, CORRECTING SINGLE EV