Analytical Equivalent Circuit Modeling for BGA in High-Speed Package

被引:23
作者
Jin, Shuai [1 ]
Liu, Dazhao [1 ]
Chen, Bichen [1 ]
Brooks, Rick [2 ]
Qiu, Kelvin [2 ]
Lim, Jane [2 ]
Fan, Jun [1 ]
机构
[1] Missouri Univ Sci & Technol, Elect Compatibil Lab, Rolla, MO 65401 USA
[2] Cisco, Santa Clara, CA 95134 USA
基金
美国国家科学基金会;
关键词
Analytical solution; ball grid array (BGA); capacitance; equivalent circuit modeling; high-speed application-specified-integrated circuit package; image theory; inductance; modal expansion; proximity effect; COMPUTATIONAL ELECTROMAGNETICS CEM; SELECTIVE VALIDATION FSV; EXTRACTION; VIAS;
D O I
10.1109/TEMC.2017.2726560
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The ball grid array (BGA) structure is the interconnection between package to printed circuit board and the discontinuity from BGA affects the performance for the whole link path in the high-speed digital system. So, it is important to accurately model the BGA structures. In current methods, the current distribution of conductors is treated as isotropic. However, the pitch size of solder balls is comparable to the diameter. The current is no longer uniformly distributed. In this paper, a fast modal-based approach is developed to accurately and efficiently capture the proximity effect. Image theory is also applied in the proposed approach to reduce the computational domain from 3-D structure to 2-D. The matrix reduction approach is applied to obtain the physical loop inductance. The lumped capacitance is obtained in [1]. A p topology equivalent circuit model for the BGA structure is built. Good agreement between the equivalent circuit model and full-wave simulation can be achieved up to 40 GHz.
引用
收藏
页码:68 / 76
页数:9
相关论文
共 43 条
[1]  
[Anonymous], 2008, P1597 IEEE
[2]   Review of Printed-Circuit-Board Level EMI/EMC Issues and Tools [J].
Archambeault, Bruce ;
Brench, Colin ;
Connor, Sam .
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2010, 52 (02) :455-461
[3]   Inductance Extraction for PCB Prelayout Power Integrity Using PMSR Method [J].
Cao, Ying S. ;
Makharashvili, Tamar ;
Cho, Jonghyun ;
Bai, Siqi ;
Connor, Samuel ;
Archambeault, Bruce ;
Jiang, Lijun ;
Ruehli, Albert E. ;
Fan, Jun ;
Drewniak, James L. .
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2017, 59 (04) :1339-1346
[4]  
Cao YS, 2016, IEEE INT SYMP ELEC, P324, DOI 10.1109/ISEMC.2016.7571667
[5]   Parasitic characteristics of BGA packages [J].
Chang, T ;
Cheng, PH ;
Huang, HC ;
Lee, RS ;
Lo, R .
IEEE SYMPOSIUM ON IC/PACKAGE DESIGN INTEGRATION - PROCEEDINGS, 1998, :124-129
[6]  
Chen B., 2017, P IEEE INT S EL COMP
[7]   Feature selective validation (FSV) for validation of computational electromagnetics (CEM). Part I - The FSV method [J].
Duffy, Alistair P. ;
Martin, Anthony J. M. ;
Orlandi, Antonio ;
Antonini, Giulio ;
Benson, Trevor M. ;
Woolfson, Malcolm S. .
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2006, 48 (03) :449-459
[8]   Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions [J].
Fan, Jun ;
Ye, Xiaoning ;
Kim, Jingook ;
Archambeault, Bruce ;
Orlandi, Antonio .
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2010, 52 (02) :392-400
[9]   An accurate equivalent circuit model of flip chip and via interconnects [J].
Ghouz, HHM ;
ElSharawy, EB .
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1996, 44 (12) :2543-2554
[10]  
Graziosi G., 2013, Proc. IEEE EMPC, P1