Time-dependent variability of high-k based MOS devices: nanoscale characterization and inclusion in circuit simulators

被引：0

作者：

Nafria, M. ^{[1
]}

Rodriguez, R. ^{[1
]}

Porti, M. ^{[1
]}

Martin-Martinez, J. ^{[1
]}

Lanza, M. ^{[1
]}

Aymerich, X. ^{[1
]}

机构：

[1] Univ Autonoma Barcelona, Dept Elect Engn, Bellaterra 08193, Spain

来源：

2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2011年

关键词：

ELECTRICAL CHARACTERIZATION; RELIABILITY; MODEL; DESIGN; IMPACT; ANALOG; OXIDE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Integrated circuit performance and/or reliability can be compromised because of the time-dependent variability observed in ultra-scaled devices, which arises from atomic scale process related variations and aging mechanisms acting during circuit operation. Therefore, extensive characterization and modeling of the nanoscale underlying phenomena is needed, so that their effects could be predicted and propagated to upper (device and circuit) levels, as dictated by the Reliability-Aware Design methodology. This paper is focused on the time-dependent shifts coming from the gate dielectric in MOS devices. Different approaches to characterize (at the nanoscale), model (at device level) and simulate (in a circuit) the related phenomena are reviewed.

引用

页数：4

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