GHz programmable dual-modulus prescaler for multi-standard wireless applications

被引：0

作者：

Ahn, HJ ^{[1
]}

Ismail, M ^{[1
]}

机构：

[1] Ohio State Univ, Dept Elect Engn, Analog VI SI Lab, Columbus, OH 43210 USA

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new and simple approach to design a programmable prescaler for wireless,applications is presented. Employing an expanded ring counter chain and a de-multiplexer in the counter loop results in an accurate frequency division and can provide various frequency-division ratios. The ring counter is implemented with true-single-phase(TSPC) type DFF and PTL(Pass Transistor Logic) type demultiplexer to enhance speed performance. PTL output is bootstrapped. With 0.5um CMOS technology and 3.3/5-V supply, the prescaler is aimed for GSM900/CDMA applications in this paper. The proposed prescaler structure can be adopted for multi-standard wireless applications covering DCS1800, WCDMA, and BLUETOOTH.

引用

页码：137 / 140

页数：4

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