Effect of Interface Traps and Oxide Charge on Drain Current Degradation in Tunneling Field-Effect Transistors

被引:62
作者
Huang, X. Y. [1 ]
Jiao, G. F. [1 ]
Cao, W. [1 ]
Huang, D. [1 ]
Yu, H. Y. [2 ,3 ]
Chen, Z. X. [2 ,3 ]
Singh, N. [2 ]
Lo, G. Q. [2 ]
Kwong, D. L. [2 ]
Li, Ming-Fu [1 ]
机构
[1] Fudan Univ, Sch Microelect, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
[2] ASTAR, Inst Microelect, Singapore 117685, Singapore
[3] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
基金
中国国家自然科学基金;
关键词
Device reliability; drain current degradation; interface traps; oxide charge; TCAD simulation; tunneling field-effect transistor (TFET); FET;
D O I
10.1109/LED.2010.2050456
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this letter, we report for the first time the degradation mechanism of drain current in tunneling field-effect transistors (TFETs). Using positive-bias and hot-carrier (HC) stress experiments and TCAD simulation, we show that the drain current degradation is mainly induced by the interface traps and/or oxide charge located above the tunneling region, causing reduction of tunneling field and tunneling current. The interface traps mainly induce the degradation in transconductance, while the oxide charge essentially causes a threshold-voltage shift in TFETs. The results show that the interface-trap generation is dominant under a positive-bias stress, while the oxide-charge creation is important under an HC stress in n-TFETs.
引用
收藏
页码:779 / 781
页数:3
相关论文
共 14 条
[1]   A simulation approach to optimize the electrical parameters of a vertical tunnel FET [J].
Bhuwalka, KK ;
Schulze, J ;
Eisele, I .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (07) :1541-1547
[2]   Double-gate tunnel FET with high-κ gate dielectric [J].
Boucart, Kathy ;
Mihai Ionescu, Adrian .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733
[3]   Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs [J].
Boucart, Kathy ;
Riess, Walter ;
Ionescu, Adrian Mihai .
IEEE ELECTRON DEVICE LETTERS, 2009, 30 (06) :656-658
[4]   Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires [J].
Chen, Z. X. ;
Yu, H. Y. ;
Singh, N. ;
Shen, N. S. ;
Sayanthan, R. D. ;
Lo, G. Q. ;
Kwong, D. -L. .
IEEE ELECTRON DEVICE LETTERS, 2009, 30 (07) :754-756
[5]   Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].
Choi, Woo Young ;
Park, Byung-Gook ;
Lee, Jong Duk ;
Liu, Tsu-Jae King .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745
[6]   A Rigorous Study of Measurement Techniques for Negative Bias Temperature Instability [J].
Grasser, Tibor ;
Wagner, Paul-Juergen ;
Hehenberger, Philipp ;
Goes, Wolfgang ;
Kaczer, Ben .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2008, 8 (03) :526-535
[7]   ZENER TUNNELING IN SEMICONDUCTORS [J].
KANE, EO .
JOURNAL OF PHYSICS AND CHEMISTRY OF SOLIDS, 1959, 12 (02) :181-188
[8]  
Kim SH, 2009, 2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P178
[9]  
Krishnamohan T, 2008, INT EL DEVICES MEET, P947
[10]  
*SYN INC, 2009, TAUR MED MED US GUID