A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders

Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are a and beta recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing. In this brief, a novel relation existing between the a and beta metrics is introduced, leading to a novel add-compare-select (ACS) architecture. The proposed technique can be applied to both the precise approximation of log-MAP and max-log-MAP ACS architectures. The proposed ACS design, which is implemented in a 0.13-mu m CMOS technology and customized for the LTE standard, results in, at most, 18.1% less area compared with the reported designs to date while maintaining the same throughput level.