Exact distribution of the max/min of two Gaussian random variables

被引：136

作者：

Nadarajah, Saralees ^{[1
]}

Kotz, Samuel ^{[2
]}

机构：

[1] Univ Manchester, Manchester M60 1QD, Lancs, England

[2] George Washington Univ, Washington, DC 20052 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2008年 / 16卷 / 02期

关键词：

maximum; minimum; moment generating function (MGF); moments; probability density function (pdf); statistical static time analysis (SSTA);

D O I：

10.1109/TVLSI.2007.912191

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Maximum and minimum of correlated Gaussian random variables arise naturally with respect to statistical static time analysis. It appears, however, that only approximations have been used in the recent literature to study the distribution of the max/min of correlated Gaussian random variables. In this paper, we would like to point out that the statistics literature has long established simple expressions for the exact distribution of the max/min. We provide some of the known expressions for the following: the probability density function, moment generating function, and the moments. We also provide two simple programs for computing the probability density functions of the max/min and an illustration of the results to statistical static time analysis.

引用

页码：210 / 212

页数：3

共 13 条

[1] Estimation of FMAX and ISB in microprocessors [J].

Abulafia, Y ;

Kornfeld, A .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (10) :1205-1209

[2] IDENTIFIABILITY OF MULTI-NORMAL AND OTHER DISTRIBUTIONS UNDER COMPETING RISKS MODEL [J].

BASU, AP ;

GHOSH, JK .

JOURNAL OF MULTIVARIATE ANALYSIS, 1978, 8 (03) :413-429

[3] Switch-factor based loop RLC modeling for efficient timing analysis [J].

Cao, Y ;

Yang, XD ;

Huang, XJ ;

Sylvester, D .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (09) :1072-1078

[4] Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion [J].

Cao, Y ;

Huang, XJ ;

Chang, NH ;

Lin, S ;

Nakagawa, OS ;

Xie, WZ ;

Sylvester, D ;

Hu, CM .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (06) :799-805

[5]

David H.A., 1970, ORDER STAT

[6] Toward architecture-based test-vector generation for timing verification of fast parallel multipliers [J].

Eriksson, Henrik ;

Larsson-Edefors, Per ;

Eckerbert, Daniel .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (04) :370-379

[7]

IHAKA R, 1996, J COMPUTATIONAL GRAP, V15, P299

[8]

NAGARAJA HN, 1982, SCANDINAVIAN ACTUARI, P188

[9] Efficient logic-level timing analysis using constraint-guided critical path search [J].

Oh, CH ;

Mercer, MR .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1996, 4 (03) :346-355

[10]

*R DEV COR TEAM, 1990, LANG ENV STAT COMP R

← 1 2 →