Si GAA NW FETs threshold voltage evaluation

被引：3

作者：

Dobrescu, Dragos ^{[1
]}

Cretu, Bogdan ^{[2
]}

Simoen, Eddy ^{[3
]}

Veloso, Anabela ^{[3
]}

Voicu-Spineanu, Andrei ^{[1
]}

Dobrescu, Lidia ^{[1
]}

机构：

[1] Univ Politehn Bucuresti, Bucharest, Romania

[2] Normandie Univ, ENSICAEN, UNICAEN, CNRS,GREYC, F-14000 Caen, France

[3] Imec, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

SOLID-STATE ELECTRONICS | 2022年 / 194卷

关键词：

Nanowires; GAA; Threshold voltage; EXTRACTION;

D O I：

10.1016/j.sse.2022.108317

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Semiconductor devices technology evolved from MOSFETs planar architecture to FinFETs and Si Gate-AllAround Nanowires (Si GAA NW) FETs structural design. This evolution has continuously decreased the values of transistors threshold voltage and extraction method errors become very important. Different methods for threshold voltage determination will be evaluated in this paper using measured data of GAA NW FETs integrated on a Silicon on Insulator (SOI) substrate, operated both in linear and saturation regions. Differences from the threshold voltage extracted values are studied in this paper.

引用

页数：4

共 10 条

[1] Threshold voltage extraction methods for MOS transistors
Dobrescu, L
Petrov, M
Dobrescu, D
Ravariu, C
[J]. 2000 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, CAS 2000 PROCEEDINGS, 2000, : 371 - 374
[2] New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs
Fleury, Dominique
Cros, Antoine
Brut, Hugues
Ghibaudo, Gerard
[J]. 2008 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, CONFERENCE PROCEEDINGS, 2008, : 160 - +
[3] NEW METHOD FOR THE EXTRACTION OF MOSFET PARAMETERS
GHIBAUDO, G
[J]. ELECTRONICS LETTERS, 1988, 24 (09) : 543 - 545
[4] Extraction of the threshold voltage of MOSFETs: an overview
Liou, JJ
Ortiz-Conde, A
Sanchez, FG
[J]. 1997 IEEE HONG KONG ELECTRON DEVICES MEETING, PROCEEDINGS, 1997, : 31 - 38
[5] Mourrain C., 2000, ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095), P181, DOI 10.1109/ICMTS.2000.844428
[6] Revisiting MOSFET threshold voltage extraction methods
Ortiz-Conde, Adelmo
Garcia-Sanchez, Francisco J.
Muci, Juan
Barrios, Alberto Teran
Liou, Juin J.
Ho, Ching-Sung
[J]. MICROELECTRONICS RELIABILITY, 2013, 53 (01) : 90 - 104
[7] Toward a demonstration of the non-linear electrical conduction law
Rusu, A
[J]. 2001 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOL 1 & 2, PROCEEDINGS, 2001, : 413 - 415
[8] Impact of fin width on digital and analog performances of n-FinFETs
Subramanian, V.
Mercha, A.
Parvais, B.
Loo, J.
Gustin, C.
Dehan, M.
Collaert, N.
Jurczak, M.
Groeseneken, G.
Sansen, W.
Decoutere, S.
[J]. SOLID-STATE ELECTRONICS, 2007, 51 (04) : 551 - 559
[9] Thean A. V.-Y, 2015, 2015 Symposium on VLSI Technology, pT26, DOI 10.1109/VLSIT.2015.7223689
[10] Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: on Gate Integrity and Device Characteristics
Veloso, A.
Cho, M. J.
Simoen, E.
Hellings, G.
Matagne, P.
Collaert, N.
Thean, A.
[J]. DIELECTRICS FOR NANOSYSTEMS 7: MATERIALS SCIENCE, PROCESSING, RELIABILITY, AND MANUFACTURING, 2016, 72 (02): : 85 - 95

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