An approach to unified phase compiler by use of 3-D representation space

被引：0
|
作者：
Miyoshi, T [1 ]
Sugino, N [1 ]
机构：
[1] Tokyo Inst Technol, Dept Adv Appl Elect, Midori Ku, Yokohama, Kanagawa 2268502, Japan
来源：
TENCON 2004 - 2004 IEEE REGION 10 CONFERENCE, VOLS A-D, PROCEEDINGS: ANALOG AND DIGITAL TECHNIQUES IN ELECTRICAL ENGINEERING | 2004年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A novel unified phase computer framework for embedded VLIWs and DSPs is shown. In this compiler a given program is represented in 3-D representation space, which enables to estimate required resources and elapsed time quantatively. Transformation of 3D representation graph which corresponds to an optimization method for specific processor architecture is also proposed The proposal compiler and the optimization methods are compared with ordinary compiler in terms of their generated codes, and hence they are proved to be effective.
引用
收藏
页码：B349 / B352
页数：4
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