A 30-MHz Voltage-Mode Buck Converter Using Delay-Line-Based PWM Control

被引:27
作者
Huang, Qiwei [1 ,2 ]
Zhan, Chenchang [2 ]
Burm, Jinwook [1 ]
机构
[1] Sogang Univ, Dept Elect Engn, Seoul 04107, South Korea
[2] Southern Univ Sci & Technol, Dept Elect & Elect Engn, Shenzhen 518055, Peoples R China
基金
中国国家自然科学基金; 新加坡国家研究基金会;
关键词
Buck; dc-dc converter; high switching frequency; voltage-mode control; voltage-to-delay; voltage-to-duty-cycle (V2D); type-II compensator; charge pump; time-based; delay-line-based; DC-DC CONVERTER;
D O I
10.1109/TCSII.2017.2764048
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 30-MHz voltage-mode buck converter using a delay-line-based pulse-width-modulation controller is proposed in this brief. Two voltage-to-delay cells are used to convert the voltage difference to delay-time difference. A charge pump is used to charge or discharge the loop filter, depending on whether the feedback voltage is larger or smaller than the reference voltage. A delay-line-based voltage-to-duty-cycle (V2D) controller is used to replace the classical ramp-comparator-based V2D controller to achieve wide duty cycle. A type-II compensator is implemented in this design with a capacitor and resistor in the loop filter. The prototype buck converter was fabricated using a 0.18-mu m CMOS process. It occupies an active area of 0.834 mm(2) including the testing PADs. The tunable duty cycle ranges from 11.9%-86.3%, corresponding to 0.4 V-2.8 V output voltage with 3.3 V input. With a step of 400 mA in the load current, the settling time is around 3 mu s. The peak efficiency is as high as 90.2% with 2.4 V output and the maximum load current is 800 mA.
引用
收藏
页码:1659 / 1663
页数:5
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