Superjunction power LDMOS on partial SOI platform

被引：30

作者：

Chen, Yu ^{[1
]}

Buddharaju, Kavitha D. ^{[2
]}

Liang, Yung C. ^{[1
]}

Samudra, Ganesh S. ^{[1
]}

Feng, Han Hua ^{[2
]}

机构：

[1] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore 119260, Singapore

[2] Inst Microelect, Singapore 117684, Singapore

来源：

PROCEEDINGS OF THE 19TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS | 2007年

关键词：

D O I：

10.1109/ISPSD.2007.4294961

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Superjunction power LDMOS device implemented on the bulk Si substrate suffers from the substrate-assisted depletion (SAD) effect, which causes the charge imbalance, and thus limits the device performance. A new SJ-LDMOS structure integrated on the partial SOI (PSOI) platform is proposed in this paper, which eliminates the SAD completely and enables the making of SJ-LDMOS on bulk silicon substrate without sacrificing its electrical and thermal performance. The PSOI SJ-LDMOS was fabricated and characterized. The tested PSOI SJ-LDMOS exhibits a specific on-state resistance of 1.01m Omega center dot cm(2) while the breakdown voltage is 72.3V.

引用

页码：177 / +

页数：2

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