A parallel architecture of interpolated timing recovery for high-speed data transfer rate and wide capture-range

被引：1

作者：

Higashino, Satoru ^{[1
]}

Kobayashi, Shoei ^{[1
]}

Yamagami, Tamotsu ^{[1
]}

机构：

[1] Sony Corp, Video Business Grp, Signal Proc Dev Dept, Storage Syst Dev Div, Gotenyama Tec 5-1-12 Kitashinagawa, Tokyo 1410001, Japan

来源：

OPTICAL DATA STORAGE 2007 | 2007年 / 6620卷

关键词：

PLL; ITR; modulo-selector; pipeline delay; loop-delay; frequency detector;

D O I：

10.1117/12.738923

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

High data transfer rate has been demanded for data storage devices along increasing the storage capacity. In order to increase the transfer rate, high-speed data processing techniques in read-channel devices are required. Generally, parallel architecture is utilized for the high-speed digital processing. We have developed a new architecture of Interpolated Timing Recovery (ITR) to achieve high-speed data transfer rate and wide capture-range in read-channel devices for the information storage channels. It facilitates the parallel implementation on large-scale-integration (LSI) devices.

引用

页数：6