Deep learning acceleration based on in-memory computing

被引:23
作者
Eleftheriou, E. [1 ]
Le Gallo, M. [1 ]
Nandakumar, S. R. [1 ]
Piveteau, C. [1 ]
Boybat, I [1 ]
Joshi, V [1 ]
Khaddam-Aljameh, R. [1 ]
Dazzi, M. [1 ]
Giannopoulos, I [1 ]
Karunaratne, G. [1 ]
Kersting, B. [1 ]
Stanisavljevic, M. [1 ]
Jonnalagadda, V. P. [1 ]
Ioannou, N. [1 ]
Kourtis, K. [1 ]
Francese, P. A. [1 ]
Sebastian, A. [1 ]
机构
[1] IBM Res Zurich, CH-8803 Ruschlikon, Switzerland
关键词
PHASE-CHANGE MEMORY; NETWORK;
D O I
10.1147/JRD.2019.2947008
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Performing computations on conventional von Neumann computing systems results in a significant amount of data being moved back and forth between the physically separated memory and processing units. This costs time and energy, and constitutes an inherent performance bottleneck. In-memory computing is a novel non-von Neumann approach, where certain computational tasks are performed in the memory itself. This is enabled by the physical attributes and state dynamics of memory devices, in particular, resistance-based nonvolatile memory technology. Several computational tasks such as logical operations, arithmetic operations, and even certain machine learning tasks can be implemented in such a computational memory unit. In this article, we first introduce the general notion of in-memory computing and then focus on mixed-precision deep learning training with in-memory computing. The efficacy of this new approach will be demonstrated by training the MNIST multilayer perceptron network achieving high accuracy. Moreover, we show how the precision of in-memory computing can be further improved through architectural and device-level innovations. Finally, we present system aspects, such as high-level system architecture, including core-to-core interconnect technologies, and high-level ideas and concepts of the software stack.
引用
收藏
页数:18
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