Traditional IC packaging requires chips to be assembled at the same level, while recently thrived 2.5D/3D IC packaging utilizes skyscraper approach to stack various types of chips with diverse functions occupying similar footprint, and this approach not only can reduce overall package size, but also can improve electrical interconnection performance. The primary difference between 2.5D/3D IC lies in the implementation of medium wafer with Through Silicon Vias (TSV), called Through Silicon Interposer (TSI). Although 2.5D IC packaging possesses the advantages of low power consumption, high data bandwidth, great electrical performance, and miniaturized form factor, the challenges of huge investment required on technology development and process manufacturing comparing to traditional 2D IC can't be ignored. Therefore, numerous innovative concepts have been proposed to reduce the cost on TSI fabrication, including but not limited to, different method of electrical interconnection, cheaper interposer utilization from material point of view, or even reconsideration of the necessity of interposer. One of the latest approaches is to utilize Fan-Out (FO) configuration to fully remove the requirement of interposer and use Epoxy Molding Compound (EMC) not only as encapsulation of functional dies but also as structure supporter for further assembly processes. The above approach utilizes multi-layer structure composed of passivaton (PSV) layers and Re-Distribution Layers (RDL) on a carrier as frontside process supporter, and subsequent compound molding process is implemented to support backside process after the removal of carrier mentioned herein. For multiple processes and materials involved in fabricating diverse kinds of packages, one of the most important technical difficulties is warpage control. Since warpage behavior of the multi-layer structure directly influences the workability of both bumping and assembly processes, it's extremely crucial to control warpage in advance to ensure smooth subsequent wafer handling and processing afterwards. In order to have desirable warpage at final stage, the material properties and mechanical behaviors of individual materials within this multi-layer structure should be further investigated and characterized. There were much efforts dedicated on the warpage characterization of different types of composite structures in the past few years, and we have also demonstrated our research progress previously regarding warpage control from numerous diverse factors at bumping process stage, including carrier types, PSV layer material types, PSV layer thickness, PSV layer quantities, and RDL pattern density. These crucial factors have been discovered and proven to affect warpage to a different extent at bumping process stage. In our latest studies, the scope of warpage characterization is further expanded and widened and specifically focused on post-bumping assembly processes, including compound molding and grinding process. The parameters of EMC, including but not limited to, material type, Coefficients of Thermal Expansion (CTE), thickness, shrinkage ratio, and EMC ratio within the whole package. The correlation between warpage and these factors are elaborated and discussed in this paper. With these findings, wafer warpage of the entire composite structure composed of PSV films, RDLs, and EMC are characterized and comprehensive understanding about the effects of different factors can be obtained and thus assist us in warpage modeling for different types of newly-developed innovative packages in the years to come.
