A 57mW 10-bit 80-MS/s pipeline ADC adopting improved power optimization approach

被引：1
作者：
Li, Bo [1 ]
Li, Zheying [2 ]
Li, Yuemei [1 ]
Wang, Chunlei [1 ]
机构：
[1] Beijing Jiaotong Univ, Sch Elect Engn, Beijing 100044, Peoples R China
[2] Beijing Union Univ, Informat Sch, Beijing 100044, Peoples R China
来源：
ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年
关键词：
D O I：
10.1109/ICASIC.2007.4415706
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An improved power optimization algorithm is presented to guide power-driven design of pipeline ADC in this paper. Five options constitute overall procedure including stage resolution distribution, capacitor scaling, stage current control, stage circuit adoption and the final validation. Using the optimization approach, a 0.18-mu m 10-bit 80-MS/s CMOS prototype achieves 58.1dB SNDR, 60.14dB SFDR under 40MHz input signal, its DNL and INL within +0.69/-0.6 and +0.75/-1.05LSB respectively. The chip consumes 57mW at 1.8-V power supply and occupies 0.567mm(2).
引用
收藏
页码：616 / 619
页数：4
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