Implementation of Single Precision Floating Point Multiplier using Karatsuba Algorithm

This paper presents an efficient floating point multiplier using Karatsuba algorithm. Digital signal processing algorithms and media applications use a large number of multiplications, which is both time and power consuming. We have used IEEE 754 format for binary representation of the floating point numbers. Verilog HDL is used to implement Karatsuba multiplication algorithm which is technology independent pipelined design. This multiplier implements the significant multiplication along with sign bit and exponent computations. Three stage pipelining is being used in the design with the latency of 8 clock cycles. In this design, the mantissa bits are divided into three parts of particular bit width in such a way so that the multiplication can be done using the standard multipliers available in FPGA cyclone II device family and synthesized using Altera-Quartus II.