Variability in nanometer CMOS: Impact, analysis, and minimization

被引：44
作者：
Sylvester, Dennis [1 ]
Agarwal, Kanak [2 ]
Shah, Saumil [1 ]
机构：
[1] Univ Michigan, Ann Arbor, MI 48109 USA
[2] IBM Corp, Austin Res Labs, Austin, TX 78758 USA
来源：
INTEGRATION-THE VLSI JOURNAL | 2008年 / 41卷 / 03期
关键词：
D O I：
10.1016/j.vlsi.2007.09.001
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Variation is a significant concern in nanometer-scale CMOS due to manufacturing equipment being pushed to fundamental limits, particularly in lithography. In this Paper, we review recent work in coping with variation, through both improved analysis and optimization. We describe techniques based on integrated circuit manufacturing, circuit design strategies, and mathematics and statistics. We then go on to discuss trends in this area, and a future technology outlook with an eye towards circuit and CAD-solutions to growing levels of variation in underlying device technologies. (C) 2007 Elsevier B.V. All rights reserved.
引用
收藏
页码：319 / 339
页数：21
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