LDPC Codes for Low-Complexity Analog Decoders

被引：0

作者：

Zheng, Hao ^{[1
]}

Ding, Xuhui ^{[1
]}

Wang, Zhiyuan ^{[1
]}

Li, Yimin ^{[2
]}

Luo, Haikun ^{[3
]}

机构：

[1] Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China

[2] Beijing Inst Remote Sensing Equipment, Beijing, Peoples R China

[3] Sci & Technol Elect Informat Control Lab, Chengdu 610036, Peoples R China

来源：

PROCEEDINGS OF THE 2015 10TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND NETWORKING IN CHINA CHINACOM 2015 | 2015年

关键词：

LDPC codes; Low-complexity analog decoders; Factor graphs; Identical building block; PROPAGATION; VLSI;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Compared with their digital counterparts, LDPC analog decoders own higher power efficiency which is suitable for low-power-consumptions applications. However, the high designing complexity of analog decoders with long block length has impeded their real-world applications. This paper presents a method to construct LDPC codes that can lower the designing complexity significantly by using identical models to form the whole decoder, as well as rules that codes should satisfy. Simulation results show that the proposed LDPC codes could lower the designing complexity with little performance lose and have better error-correcting performance than codes in CCSDS standard.

引用

页码：167 / 171

页数：5

共 16 条

[1]

ABOLFAZLI AR, 2013, SOL STAT CIRC C A SS, P181

[2] A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder [J].

Blanksby, AJ ;

Howland, CJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (03) :404-412

[3] Design considerations leading to the development of good π-rotation LDPC codes [J].

Echard, R ;

Chang, SC .

IEEE COMMUNICATIONS LETTERS, 2005, 9 (05) :447-449

[4]

Frey M., 1999, IEEE INT S CIRC SYST, pI

[5] LOW-DENSITY PARITY-CHECK CODES [J].

GALLAGER, RG .

IRE TRANSACTIONS ON INFORMATION THEORY, 1962, 8 (01) :21-&

[6] A 100 pJ/bit, (32,8) CMOS Analog Low-Density Parity-Check Decoder Based on Margin Propagation [J].

Gu, Ming ;

Chakrabartty, Shantanu .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (06) :1433-1442

[7] Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes [J].

Hemati, S ;

Banihashemi, AH .

IEEE TRANSACTIONS ON COMMUNICATIONS, 2006, 54 (01) :61-70

[8] A 0.18-μm CMOS analog min-sum iterative decoder for a (32,8) low-density parity-check (LDPC) code [J].

Hemati, Saied ;

Banihashemi, Amir H. ;

Plett, Calvin .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (11) :2531-2540

[9]

Ke X., 2011, J SW U NATL NATURAL, V37, P703

[10] Factor graphs and the sum-product algorithm [J].

Kschischang, FR ;

Frey, BJ ;

Loeliger, HA .

IEEE TRANSACTIONS ON INFORMATION THEORY, 2001, 47 (02) :498-519

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