Hardware design of LIF with Latency neuron model with memristive STDP synapses

被引：24

作者：

Acciarito, Simone ^{[1
]}

Cardarilli, Gian Carlo ^{[1
]}

Cristini, Alessandro ^{[1
]}

Di Nunzio, Luca ^{[1
]}

Fazzolari, Rocco ^{[1
]}

Khanal, Gaurav Mani ^{[1
]}

Re, Marco ^{[1
]}

Susi, Gianluca ^{[1
,2
]}

机构：

[1] Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy

[2] Tech Univ Madrid, Ctr Biomed Technol, Lab Cognit & Computat Neurosci UCM UPM, Madrid, Spain

来源：

INTEGRATION-THE VLSI JOURNAL | 2017年 / 59卷

关键词：

Leaky Integrate-and-Fire with Latency (LIFL); Neuron; Synapse; STDP; Memristor; Neuromorphic system; Analog VLSI; SPIKING NEURONS; NETWORKS; PLASTICITY; SIMULATION;

D O I：

10.1016/j.vlsi.2017.05.006

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks.

引用

页码：81 / 89

页数：9

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