An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

被引:16
作者
Ho, CS
Huang, KY
Tang, M
Liou, JJ [1 ]
机构
[1] Univ Cent Florida, Dept Elect & Comp Engn, Orlando, FL 32816 USA
[2] ProMOS Technol, R&D Device Div, Hsinchu 300, Taiwan
关键词
D O I
10.1016/j.microrel.2004.10.007
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design). (c) 2004 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1144 / 1149
页数:6
相关论文
共 12 条
[1]  
*AV CORP, 2001, SUPR MED MAN
[2]  
Bouhdada A, 2001, INT C MICROELECTRON, P27
[3]   Direct lateral profiling of both interface traps and oxide charge in thin gate MOSFET devices [J].
Chen, C ;
Ma, TP .
1996 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1996, :230-231
[4]   HOT-ELECTRON-INDUCED MOSFET DEGRADATION - MODEL, MONITOR, AND IMPROVEMENT [J].
HU, CM ;
TAM, SC ;
HSU, FC ;
KO, PK ;
CHAN, TY ;
TERRILL, KW .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (02) :375-385
[5]   The threshold-voltage model of MOSFET devices with localized interface charge [J].
Jean, YS ;
Wu, CY .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (03) :441-447
[6]  
KACER F, 2001, P 13 INT C MICR MOR, P43
[7]   PHYSICAL MODEL OF DRAIN CONDUCTANCE, GD, DEGRADATION OF NMOSFETS DUE TO INTERFACE STATE GENERATION BY HOT-CARRIER INJECTION [J].
KURACHI, I ;
HWANG, N ;
FORBES, L .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (06) :964-969
[8]   A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET's [J].
Lee, RGH ;
Su, JS ;
Chung, SS .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (01) :81-89
[9]   THRESHOLD VOLTAGE MODEL FOR DEEP-SUBMICROMETER MOSFETS [J].
LIU, ZH ;
HU, CM ;
HUANG, JH ;
CHAN, TY ;
JENG, MC ;
KO, PK ;
CHENG, YC .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (01) :86-95
[10]  
SHABDE S, 1998, SOLID STATE ELECT, V31, P1603