A Power-Line Interference Canceler Based on Sliding DFT Phase Locking Scheme for ECG Signals

被引:41
|
作者
Mishra, Sarita [1 ]
Das, Debasmit [2 ]
Kumar, Roshan [3 ]
Sumathi, Parasuraman [2 ]
机构
[1] Graph Era Hill Univ, Dept Elect & Commun Engn, Bhimtal 247667, India
[2] IIT Roorkee, Dept Elect Engn, Roorkee 247667, Uttar Pradesh, India
[3] IIT Roorkee, Dept Earthquake Engn, Roorkee 247667, Uttar Pradesh, India
关键词
Adaptive filters; discrete Fourier transform (DFT); electrocardiography; field programmable gate arrays (FPGAs); interference cancelation; phase locked loop; IIR NOTCH FILTER; ELECTROCARDIOGRAPHY; ELIMINATION; SUPPRESSION; ALGORITHM; REMOVAL;
D O I
10.1109/TIM.2014.2335920
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A power-line interference (PLI) removal method is proposed based on a previously published sliding discrete Fourier transform (SDFT) phase locking scheme (PLL), which extracts the nonstationary sinusoids from the electrocardiogram (ECG) signal. The proposed PLI canceler consists of SDFT PLL as a vital element, which can track the variation in center frequency of the PLI either 50 or 60 Hz. The PLI canceler involves the adaptive sampling frequency control in which the sampling frequency of SDFT filter is adaptively adjusted according to the center frequency variation of the interference. Since the in-phase and quadrature components of SDFT filter can provide instantaneous sinusoidal and cosinusoidal interference signals, the SDFT PLL is capable of tracking amplitude, phase, and frequency of the interference. Additional resonators of different bin indices are augmented with SDFT PLL to handle the dominant odd harmonics of PLI. Furthermore, the SDFT PLL is cascaded with another SDFT bin to eliminate the baseline wander present in the real-time ECG signal. The adaptive PLI canceler based on SDFT PLL offers the tracking capability of variant PLI, attenuation of 40 dB, less acquisition time of 0.2 s for a variant PLI of +/- 5 Hz, removal of dominant odd harmonics, and baseline wander with expense of sampling frequency. Experimental results prove the efficacy of the proposed method in nonstationary sinusoidal interference extraction. Experimental investigation on SDFT PLL using field programmable gate array demonstrates the feasibility of digital implementation of the proposed algorithm.
引用
收藏
页码:132 / 142
页数:11
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