Gate current modeling for MOSFETs

We describe a set of models suitable for the two- and three-dimensional simulation of tunneling in logic and non-volatile MOS devices. The crucial modeling topics are comprehensively discussed. This comprises the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, the modeling of static and transient defectassisted tunneling, and the modeling of dielectric degradation and breakdown. We propose a set of models to link the gate leakage to the creation of traps in the dielectric layer, the threshold voltage shift, and eventual dielectric breakdown. The simulation results are compared to commonly used compact models and measurements of logic and non-volatile memory devices.