A high-performance CMOS charge-pump for phase-locked loops

In order to improve the performance of the existing CMOS charge pumps (CPs), a systematical analysis of the existing CMOS CPs is presented. The nonideal effects such as mismatches, switch errors in CMOS CPs are quantitatively or qualitatively analyzed. Based on the circuit architecture, both classification and comparison are made. An improved CMOS single-ended CP is designed in SMIC 0.18-mu m CMOS technology with 1.8-V supply voltage. In the CP, the switches are located at the source of the current mirror, and these switches are implemented using transmission gates driven by a couple of complementary clock signals. In addition, a large bypass capacitor is added to the CP. These circuits are used to make the CP avoid the switch errors. On the other hand, the charging current I-UP and the discharging current I-DN are both derived from the same supply-independent reference current source, and a high-gain folded-cascode operational amplifier is used to make the CP evade the sourcing/sinking current mismatch caused by the channel-length modulation effect of the current mirrors. The proposed CP only occupies an active area of 100 mu mx150 mu m. Post-simulation results reveal that the proposed CP has a wide output range, from 0.25 V to 1.62V, and near perfect current matching characteristic. The current matching precision is better than 0.0105%.