Automating the design of SOCs using cores

被引：44

作者：

Bergamaschi, RA

Bhattacharya, S

Wagner, R

Fellenz, C

Muhlada, M

White, F

Lee, WR

Daveau, JM

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

[2] Intel Corp, Santa Clara, CA 95051 USA

[3] Cisco Syst, Res Triangle Pk, NC USA

[4] ST Microelect, R&D Ctr, Embedded Syst Tools Team, Crolles, France

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2001年 / 18卷 / 05期

关键词：

D O I：

10.1109/54.953270

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Assembling a system on a chip using IP blocks is an error-prone, labor-intensive, and time-consuming process. Emerging high-level tools can help by automating many of the design tasks.

引用

页码：32 / 45

页数：14

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