Scaling analysis of interconnectivity and crosstalk in VLSI circuits

被引：1
|
作者：
Zheng, LR [1 ]
Tenhunnen, H [1 ]
机构：
[1] Royal Inst Technol, Dept Elect, Elect Syst Design Lab, S-16440 Stockholm, Sweden
来源：
ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING | 1998年
关键词：
D O I：
10.1109/EPEP.1998.733905
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper analyses the interconnectivity and crosstalk of submicron wires used for VLSI interconnects. The maximum interconnectivity is optimized under some fundamental constraints such as wire geometries and crosstalk etc.
引用
收藏
页码：124 / 127
页数：4
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