Gzippo: Highly-compact Processing-In-Memory Graph Accelerator Alleviating Sparsity and Redundancy

被引:1
|
作者
Li, Xing [1 ]
Ausavarungnirun, Rachata [2 ]
Liu, Xiao [3 ]
Liu, Xueyuan [1 ]
Zhang, Xuan [1 ]
Lu, Heng [1 ]
Song, Zhuoran [1 ]
Jing, Naifeng [1 ]
Liang, Xiaoyao [1 ]
机构
[1] Shanghai Jiao Tong Univ, Shanghai, Peoples R China
[2] King Mongkuts Univ Technol North Bangkok, Bangkok, Thailand
[3] Bytedance US Lab, Mountain View, CA USA
来源
2022 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, ICCAD | 2022年
基金
中国国家自然科学基金; 国家重点研发计划;
关键词
graph computation; processing-in-memory; sparsity; redundancy; RRAM; PERFORMANCE; ANALYTICS;
D O I
10.1145/3508352.3549372
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Graph application plays a significant role in real-world data computation. However, the memory access patterns become the performance bottleneck of the graph applications, which include low compute-to-communication ratio, poor temporal locality, and poor spatial locality. Existing RRAM-based processing-in-memory accelerators reduce the data movements but fail to address both sparsity and redundancy of graph data. In this work, we present Gzippo, a highly-compact design that supports graph computation in the compressed sparse format. Gzippo employs a tandem-isomorphic-crossbar architecture both to eliminate redundant searches and sequential indexing during iterations, and to remove sparsity leading to non-effective computation on zero values. Gzippo achieves a 3.0x (up to 17.4x) performance speedup, 23.9x (up to 163.2x) energy efficiency over state-of-the-art RRAM-based PIM accelerator, respectively.
引用
收藏
页数:9
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