10 nm TriGate High k Underlap FinFETs: Scaling Effects and Analog Performance

被引：15

作者：

Bha, J. K. Kasthuri ^{[1
]}

Priya, P. Aruna ^{[1
]}

Joseph, H. Bijo ^{[2
]}

Thiruvadigal, D. John ^{[2
]}

机构：

[1] SRM Inst Sci & Technol, Dept Elect & Commun Engn, Chennai, Tamil Nadu, India

[2] SRM Inst Sci & Technol, Ctr Mat Sci & Nano Devices, Dept Phys & Nanotechnol, Chennai, Tamil Nadu, India

来源：

SILICON | 2020年 / 12卷 / 09期

关键词：

Tri gate FinFET; Short channel effect; High k dielectric material; Metal gate; Analog performance; WORK FUNCTION VARIABILITY; GS-DG-MOSFET; CHANNEL; SI; SIMULATION; IMPACT; MODEL; GE;

D O I：

10.1007/s12633-019-00299-y

中图分类号：

O64 [物理化学（理论化学）、化学物理学];

学科分类号：

070304 ; 081704 ;

摘要：

Nano scale devices with improved performance than the conventional CMOS devices is of great need in recent days. The paper investigates the performance of 10 nm Trigate FinFET structure with high k dielectric spacer on either side of the channel in the underlap region. The proposed structure increases the On-Off ratio (I-ON/ I-OFF) of drain current by order of 10(6) and also improves the subthreshold swing (SS). Further, it enhances the transconductance (g(m)) at the low gate voltage, raises the output conductance (g(d)) and intrinsic gain (g(m)/g(d)) proving that the device provides efficient analog performance suitable for RF applications.

引用

页码：2111 / 2119

页数：9

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