On the complexity of multiplierless direct and polyphase FIR filter structures

被引：0

作者：

Eghbali, Amir ^{[1
]}

Gustafsson, Oscar ^{[1
]}

Johansson, Hakan ^{[1
]}

Lowenborg, Per ^{[1
]}

机构：

[1] Linkoping Univ, Div Elect Syst, Dept Elect Engn, SE-58183 Linkoping, Sweden

来源：

PROCEEDINGS OF THE 5TH INTERNATIONAL SYMPOSIUM ON IMAGE AND SIGNAL PROCESSING AND ANALYSIS | 2007年

关键词：

multiple constant multiplication; multiplierless; FIR filter; complexity;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper discusses the complexity trend in different finite length impulse response (FIR) filter structures when using multiplierless (shift-and-add) realization. We derive the total number of adders required by the transposed direct form, polyphase, and reduced-complexity polyphase FIR filter structures. A comparison of the arithmetic complexities of these structures for different filter characteristics is performed. The simulation results show that considering both the high level structure and the algorithm used to realize the subfilters gives a more accurate measure of complexity comparison between different FIR filter structures.

引用

页码：200 / 205

页数：6

共 50 条

[21] Multiplication and Accumulation Co-Optimization for Low Complexity FIR Filter Implementation
Rao, Chaolin
Lou, Xin
ELECTRONICS, 2022, 11 (11)
[22] Implementation of the multiplierless parallel multiprocessor interpolating filter
Ashrafand, M.
Mahmud, R.
PROCEEDINGS OF THE 10TH INTERNATIONAL CONFERENCE ON OPTIMIZATION OF ELECTRICAL AND ELECTRONIC EQUIPMENT, VOL IV, 2006, : 103 - 108
[23] A Multiplierless Implementation of Cascade Integrator Comb Filter
Saberi, Nezam
Ahmadi, Arash
Alirezaee, Shahpour
Ahmadi, Majid
2015 INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (ISSCS), 2015,
[24] Design of Low-Power Multiplierless Linear-Phase FIR Filters
Ye, Wen Bin
Lou, Xin
Yu, Ya Jun
IEEE ACCESS, 2017, 5 : 23466 - 23472
[25] A Custom Reconfigurable Power Efficient FIR Filter
Sakthivel, R.
Mishra, Ishita
Jalke, Vrushali
Wachaspati, Asmita
PROCEEDINGS OF IEEE INTERNATIONAL CONFERENCE ON CIRCUIT, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2016), 2016,
[26] VHDL implementation of multiplierless, high performance DWT filter bank
Aswale, M. M.
Patil, R. B.
WORLD CONGRESS ON ENGINEERING 2007, VOLS 1 AND 2, 2007, : 708 - +
[27] Hybrid Structures for Low-Complexity Variable Fractional-Delay FIR Filters
Deng, Tian-Bo
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (04) : 897 - 910
[28] Implementation of a Frequency FIR Filter as 2D-FIR Filter Based on FPGA
Fakharian, Ahmad
Badr, Saeed
Abdi, Mohsen
2015 AI & ROBOTICS (IRANOPEN), 2015,
[29] A Review of FIR Filter Designs
Bansal, Bharat Naresh
Singh, Amanpreet
Bhullar, Jaskarn Singh
NETWORKING COMMUNICATION AND DATA KNOWLEDGE ENGINEERING, VOL 1, 2018, 3 : 125 - 140
[30] A 70 MHz multiplierless FIR Hilbert transformer in 0.35 μm standard CMOS library
Takahashi, Yasuhiro
Sekine, Toshikazu
Yokoyama, Michio
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2007, E90A (07) : 1376 - 1383

← 1 2 3 4 5 →