Improvement of thermal stability of via resistance in dual damascene copper interconnection

被引：39

作者：

Oshima, T ^{[1
]}

Tamaru, T ^{[1
]}

Ohmori, K ^{[1
]}

Aoki, H ^{[1
]}

Ashihara, H ^{[1
]}

Saito, T ^{[1
]}

Yamaguchi, H ^{[1
]}

Miyauchi, M ^{[1
]}

Torii, K ^{[1
]}

Murata, J ^{[1
]}

Satoh, A ^{[1
]}

Miyazaki, H ^{[1
]}

Hinode, K ^{[1
]}

机构：

[1] Hitachi Ltd, Device Dev Ctr, Ome, Tokyo 1988512, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904273

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Thermal stability of via resistance in the multilevel dual damascene Cu interconnection was investigated. The via resistance stability strongly depends on via size, via density and width of connecting Cu wires. The significant via-resistance shift was introduced by stress-induced voiding. To avoid the voiding failure, optimization of heat treatments after electroplating (EP)Cu deposition are necessary for both stability of Cu films and adhesion of barrier layer with Cu. Thermal stress balance between Cu wires and inter-level-dielectric (ILD) is also important to suppress the via degradation The dual damascene structure with lower-stress and lower-Young's modulus ILD films such as FSG can provide wider process windows for the stability of the via resistance.

引用

页码：123 / 126

页数：4

共 5 条

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