Understanding and minimizing ground bounce during mode transition of power gating structures

被引：0

作者：

Kim, S ^{[1
]}

Kosonocky, SV ^{[1
]}

Knebel, DR ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2003年

关键词：

clock gating; power gating; wake-up latency; inductive noise; ground bounce; system-on-a-chip (SOC) design;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which sleep transistors are turned on in a non-uniform stepwise manner. Our power gating structures reduce the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground. Experimental simulation results with PowerSpice fixtured in a package model demonstrate the effectiveness of the proposed power gate switching noise reduction techniques.

引用

页码：22 / 25

页数：4

共 8 条

[1] Analysis of ground bounce in deep sub-micron circuits [J].

Chang, YS ;

Gupta, SK ;

Breuer, MA .

15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, :110-116

[2]

El-Essawy W, 2002, ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P263, DOI 10.1109/LPE.2002.1029617

[3] Estimation of ground bounce effects on CMOS circuits [J].

Kabbani, A ;

Al-Khalili, AJ .

IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 1999, 22 (02) :316-325

[4] A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current [J].

Kawaguchi, H ;

Nose, K ;

Sakurai, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (10) :1498-1501

[5] Enhanced multi-threshold (MTCMOS) circuits using variable well bias [J].

Kosonocky, SV ;

Immediato, M ;

Cottrell, P ;

Hook, T ;

Mann, R ;

Brown, J .

ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN, 2001, :165-169

[6] Design method of MTCMOS power switch for low-voltage high-speed LSIs [J].

Mutoh, S ;

Shigematsu, S ;

Gotoh, Y ;

Konaka, S .

PROCEEDINGS OF ASP-DAC '99: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1999, 1999, :113-116

[7]

Pant M. D., 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477), P255, DOI 10.1109/LPE.1999.799450

[8] On-chip ΔI noise in the power distribution networks of high speed cmos integrated circuits [J].

Tang, KT ;

Friedman, EG .

13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2000, :53-57

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