FPGA realization of an OFDM frame synchronization design for dispersive channels

This paper presents an FPGA implementation of an OFDM time synchronization scheme for dispersive channels. The synchronization algorithm, adapted from the scheme in [1], is an ounbiased maximum likelihood (ML) estimator. The original estimator structure, however, is far too complex for either DSP or hardware implementation. In this paper, we simplify the synchronization algorithm and propose an efficient architecture design using only moderate circuit complexity without causing performance degradation. The design is then implemented in an Altera EP20K200 FPGA and consumes approximately 140K logic gates and 62k bits on-chip memory. The design can operate up to 28.47MHz, which means the synchronization can sustain a sample rate up to 28.47 Msamples/s.