Symbolic computation tree logic model checking of time Petri nets

被引:0
作者
Okawa, Y
Yoneda, T
机构
来源
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE | 1997年 / 80卷 / 04期
关键词
time Petri nets; CTL; symbolic model checking; region; formal verification;
D O I
10.1002/(SICI)1520-6440(199704)80:4<11::AID-ECJC2>3.0.CO;2-7
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Model checking is a technique to decide whether a system modeled by a state graph satisfies a temporal logic formula. A serious problem in model checking of practical systems is that the size of the state graphs becomes huge. One solution of this problem is symbolic model checking, in which sets of states and transition relations over states are represented and handled symbolically. This research studies symbolic model checking in which realtime systems are modeled by time Petri nets and specifications are expressed by computation tree logic formulas. As realtime systems potentially have infinite state spaces, techniques to reduce infinite state spaces to finite ones are necessary. This paper discusses a technique based on equivalence classes, called regions, of states as well as a technique to restrict the behavior of time Petri nets so that transitions fire only at integer times. The algorithm in the former approach is presented in detail and then some experimental results are shown.
引用
收藏
页码:11 / 20
页数:10
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