Numerical and Experimental Study of Fan-out Wafer Level Package Strength

被引:1
|
作者
Xu, Cheng [1 ]
Zhong, Z. W. [1 ]
Choi, W. K. [2 ]
机构
[1] Nanyang Technol Univ, Sch Mech & Aerosp Engn, Singapore, Singapore
[2] JCET STATS ChipPAC Pte Ltd, Singapore, Singapore
关键词
fan-out wafer level package; package strength; three-point bending test; finite element method; SILICON DIE STRENGTH; FRACTURE; TESTS;
D O I
10.1109/ECTC.2017.152
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Fan-out wafer level packaging technology becomes more attractive and popular in the semiconductor packaging industry. The fan-out wafer level package (FOWLP) has the feature of integrating various devices in a tiny form factor. Since the FOWLP size is compact and small, its package strength is critical to its reliability. In this work, the three-point bending test method and finite element method was used to evaluate the FOWLP strength. Two different structural FOWLP were built, and their numerical models were created. The results showed that the FOWLP experiment and simulation flexure strength results matched each other in the lower failure possibility area closely. However, the simulation results under-estimated the FOWLP failure possibility to compare with the experiment results in the upper failure possibility area.
引用
收藏
页码:2187 / 2192
页数:6
相关论文
共 50 条
  • [31] Innovative Fan-Out Wafer Level Package using Lamination Process and Adhered Si Wafer on the Backside
    Hsu, H. S.
    Chang, David
    Liu, Kenny
    Kao, Nicholas
    Liao, Mark
    Chiu, Steve
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 1384 - 1387
  • [32] A Mechanics Model for the Moisture Induced Delamination in Fan-Out Wafer-Level Package
    Chiu, Tz-Cheng
    Wu, Ji-Yen
    Liu, Wei-Te
    Liu, Chang-Wei
    Chen, Dao-Long
    Shih, MengKai
    Tarng, David
    2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020), 2020, : 1205 - 1211
  • [33] Comparison of Package-on-Package Technologies Utilizing Flip Chip and Fan-Out Wafer Level Packaging
    Lujan, Amy P.
    2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 2089 - 2094
  • [34] Thermomechanical Properties of Fan-Out Wafer Level Package with Various Chip and Mold Thickness
    Jeong, Haksan
    Myung, Woo-Ram
    Jung, Kwang-Ho
    Jung, Seung-Boo
    2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 2121 - 2126
  • [35] SLIM™, High Density Wafer Level Fan-out Package Development with Submicron RDL
    Kim, YoungRae
    Bae, JaeHun
    Chang, MinHwa
    Jo, AhRa
    Kim, Ji Hyun
    Park, SangEun
    Hiner, David
    Kelly, Michael
    Do, WonChul
    2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 8 - 13
  • [36] Die-to-Package Coupling Extraction for Fan-Out Wafer-Level-Packaging
    Peng, Yarui
    Petranovic, Dusan
    Lim, Sung Kyu
    2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,
  • [37] Newly Developed Ultra Thin Fan-Out Wafer Level Package for PoP Usage
    Shimamoto, H.
    Soga, K.
    Takemra, K.
    Yanagisawa, H.
    Asai, S.
    Kondo, K.
    Sugo, M.
    Kato, H.
    Matsuda, Y.
    2014 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP), 2014, : 30 - 33
  • [38] Stress Analysis of Typical Structure of Redistribution Layer of Fan-Out Wafer Level Package
    Zhou, Shilu
    Zhong, Cheng
    Shan, Liang
    Li, Jinhui
    He, Chuan
    Huang, Da
    Lu, Jibao
    Zhang, Guoping
    Sun, Rong
    2022 23RD INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2022,
  • [39] InFO (Wafer Level Integrated Fan-Out) Technology
    Tseng, Chien-Fu
    Liu, Chung-Shi
    Wu, Chi-Hsi
    Yu, Douglas
    2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, : 1 - 6
  • [40] Realization of the potential of fan-out wafer level packaging
    Carson, Flynn
    Advancing Microelectronics, 2010, 37 (03): : 10 - 12