Low Power 14T Hybrid Full Adder Cell

被引：0

作者：

Sugandha, Chauhan ^{[1
]}

Tripti, Sharma ^{[1
]}

机构：

[1] Chandigarh Univ Gharuan, Dept Elect & Commun Engn, Mohali, Punjab, India

来源：

PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON FRONTIERS IN INTELLIGENT COMPUTING: THEORY AND APPLICATIONS, (FICTA 2016), VOL 2 | 2017年 / 516卷

关键词：

Power consumption; Delay; Parasitic capacitance; Area; Power-delay product; CMOS; DESIGN; LOGIC;

D O I：

10.1007/978-981-10-3156-4_15

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The performance of the adder entirely influenced by the performance of its basic modules. In this paper, a new hybrid 1-bit 14 transistor full adder design is proposed. The proposed circuit has been implemented using pass gate as well as CMOS logic hence named hybrid. The main design objective for this circuit is low power consumption and full voltage swing at a low supply voltage. As a result the proposed adder cell remarkably improves the power consumption, power-delay product and has less parasitic capacitance when compared to the 16T design. It also improves layout area by 7-8 % than its peer design. All simulations are performed at 90 & 45 nm process technology on Synopsys tool.

引用

页码：151 / 160

页数：10

共 50 条

[21] A Low Power Gate Level Full Adder Module
Balasubramanian, Padmanabhan
Mastorakis, Nikos E.
PROCEEDINGS OF THE 3RD INT CONF ON APPLIED MATHEMATICS, CIRCUITS, SYSTEMS, AND SIGNALS/PROCEEDINGS OF THE 3RD INT CONF ON CIRCUITS, SYSTEMS AND SIGNALS, 2009, : 246 - +
[22] Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Bhattacharyya, Partha
Kundu, Bijoy
Ghosh, Sovan
Kumar, Vinay
Dandapat, Anup
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (10) : 2001 - 2008
[23] Design and Performance Analysis of Low-Power Hybrid Full Adder Circuit
Upadhyay, Rahul Mani
Kumar, Manish
JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2021, 16 (01): : 13 - 23
[24] Modeling and Simulation of Low Power 14 T Full Adder with Reduced Ground Bounce Noise at 45 nm Technology
Singh, Raghvendra
Akashe, Shyam
2013 STUDENTS CONFERENCE ON ENGINEERING AND SYSTEMS (SCES): INSPIRING ENGINEERING AND SYSTEMS FOR SUSTAINABLE DEVELOPMENT, 2013,
[25] Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation
Hasan, Mehedi
Hossein, Md. Jobayer
Hossain, Mainul
Zaman, Hasan U.
Islam, Sharnali
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (08) : 1464 - 1468
[26] A New Low-Power Hybrid Full Adder Using CCGDI Technique for a Portable MAC Unit
Mukherjee, Biswarup
IETE JOURNAL OF RESEARCH, 2025,
[27] A Survey on Different Modules of Low-Power High-Speed Hybrid Full Adder Circuits
Saraswat, Vivek
Kumar, Ankur
Pal, Pratosh Kumar
Nagaria, R. K.
2017 4TH IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS (UPCON), 2017, : 323 - 328
[28] Performance analysis of a low power high speed full adder
Bajpai, Paro
Mittal, Priyanka
Rana, Amita
Aneja, Bhupesh
2017 2ND INTERNATIONAL CONFERENCE ON TELECOMMUNICATION AND NETWORKS (TEL-NET), 2017, : 291 - 295
[29] Design of Low Power High Speed Full Adder Cell with XOR/XNOR Logic Gates
Alluri, Sudhakar
Dasharatha, M.
Naik, B. Rajendra
Reddy, N. S. S.
2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1, 2016, : 565 - 570
[30] A Novel Power-Aware and High Performance Full Adder Cell for Ultra-Low Power Designs
Ramireddy, Gangadhar Reddy
Ravindra, J. V. R.
2014 IEEE INTERNATIONAL CONFERENCE ON CIRCUIT, POWER AND COMPUTING TECHNOLOGIES (ICCPCT-2014), 2014, : 1121 - 1126

← 1 2 3 4 5 →