Low Power 14T Hybrid Full Adder Cell

被引：0

作者：

Sugandha, Chauhan ^{[1
]}

Tripti, Sharma ^{[1
]}

机构：

[1] Chandigarh Univ Gharuan, Dept Elect & Commun Engn, Mohali, Punjab, India

来源：

PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON FRONTIERS IN INTELLIGENT COMPUTING: THEORY AND APPLICATIONS, (FICTA 2016), VOL 2 | 2017年 / 516卷

关键词：

Power consumption; Delay; Parasitic capacitance; Area; Power-delay product; CMOS; DESIGN; LOGIC;

D O I：

10.1007/978-981-10-3156-4_15

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The performance of the adder entirely influenced by the performance of its basic modules. In this paper, a new hybrid 1-bit 14 transistor full adder design is proposed. The proposed circuit has been implemented using pass gate as well as CMOS logic hence named hybrid. The main design objective for this circuit is low power consumption and full voltage swing at a low supply voltage. As a result the proposed adder cell remarkably improves the power consumption, power-delay product and has less parasitic capacitance when compared to the 16T design. It also improves layout area by 7-8 % than its peer design. All simulations are performed at 90 & 45 nm process technology on Synopsys tool.

引用

页码：151 / 160

页数：10

共 17 条

[1] CMOS Full-Adders for Energy-Efficient Arithmetic Applications [J].