An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

被引:9
作者
Ta, Van-Thanh [1 ]
Hoang, Van-Phuc [1 ]
Pham, Van-Phu [1 ]
Pham, Cong-Kha [2 ]
机构
[1] Le Quy Don Tech Univ, Fac Radioelect Engn, 236 Hoang Quoc Viet Str, Hanoi 100000, Vietnam
[2] Univ Electrocommun, Grad Sch Informat & Engn, Chofu, Tokyo 1828585, Japan
关键词
TIADC; channel mismatch; Hadamard transform; all-digital background calibration; FPGA; BLIND CALIBRATION; COMPENSATION; ERROR; SKEW;
D O I
10.3390/electronics9010073
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC's performance.
引用
收藏
页数:13
相关论文
共 33 条
[1]  
[Anonymous], 2019, ELECTRONICS SWITZ, DOI DOI 10.3390/electronics8010056
[2]  
Benabes P, 2014, IEEE INT NEW CIRC, P49, DOI 10.1109/NEWCAS.2014.6933982
[3]  
Black W., 1980, P IEEE INT SOL STAT, VXXIII, P14
[4]   Correlation-Based Frequency-Response Mismatch Compensation of Quad-TIADC Using Real Samples [J].
Bonnetat, Antoine ;
Hode, Jean-Michel ;
Ferre, Guillaume ;
Dallet, Dominique .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62 (08) :746-750
[5]   Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs [J].
Camarero, David ;
Ben Kalaia, Karim ;
Naviner, Jean-Francois ;
Loumeau, Patrick .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (11) :3676-3687
[6]   Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters [J].
Centurelli, Francesco ;
Monsurro, Pietro ;
Trifiletti, Alessandro .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (07) :1373-1383
[7]   Blind Calibration of Timing Skew in Time-Interleaved Analog-to-Digital Converters [J].
Divi, Vijay ;
Wornell, Gregory W. .
IEEE JOURNAL OF SELECTED TOPICS IN SIGNAL PROCESSING, 2009, 3 (03) :509-522
[8]  
Doris K., 2011, 2011 IEEE International Solid-State Circuits Conference (ISSCC 2011), P180, DOI 10.1109/ISSCC.2011.5746272
[9]   A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration [J].
El-Chammas, Manar ;
Murmann, Boris .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (04) :838-847
[10]   A sample-time error compensation technique for time-interleaved ADC systems [J].
Haftbaradaran, Afshin ;
Martin, Kenneth W. .
PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, :341-344