Winner-take-all circuit using CMOS technology

被引：0
|
作者：
Oki, N [1 ]
机构：
[1] UNESP, FEIS, DEE, Sao Paulo, Brazil
来源：
1998 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS | 1999年
关键词：
D O I：
10.1109/MWSCAS.1998.759556
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).
引用
收藏
页码：568 / 570
页数：3
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