Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture

The input buffers of the current packet-switched Network-on-Chip (NoC) architectures consume a significant portion of the total power of the interconnection network. Reducing the size of input buffers would result in degraded performance, while eliminating all buffers would result in increased power at high network load. In this article, we propose DXbar: an innovative dual-crossbar design. By combining the advantages of buffered and bufferless networks, we achieve at least 20% performance improvement in terms of throughput and latency, and at least 20% power saving over buffered networks with virtual channels. Furthermore. DXbar can outperform current bufferless networks with deflecting and dropping protocols while consuming at most half of the power. (C) 2010 Elsevier B.V. All rights reserved.